Zhongheng Liu | 刘仲衡

Zhongheng Liu | 刘仲衡

Tsinghua undergraduate working on efficient multimodal AI, LLM agents, and graph learning.

5-Stage Pipelined MIPS Processor

This project implemented a five-stage pipelined MIPS processor in Verilog, covering instruction fetch, decode, execute, memory access, and write-back stages.

The processor includes hazard detection and forwarding logic to reduce pipeline stalls. I also designed custom MIPS instructions and software-level instruction decoding to drive seven-segment display logic, enabling sparse matrix multiplication results to be visualized on FPGA hardware.

Schematic preview of a five-stage pipelined MIPS processor

Highlights

  • Implemented a complete five-stage datapath with pipeline registers.
  • Added hazard detection, stall/flush control, and forwarding paths.
  • Designed custom instructions for application-specific display output.
  • Optimized timing and area, reaching a maximum clock frequency of 66.9 MHz with a CPI of 1.13.